gate level logic simulation
英 [ɡeɪt ˈlevl ˈlɒdʒɪk ˌsɪmjuˈleɪʃn]
美 [ɡeɪt ˈlevl ˈlɑːdʒɪk ˌsɪmjuˈleɪʃn]
网络 门级逻辑模拟
双语例句
- The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。